On 2023/5/12 14:47, Conor Dooley wrote: > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: >> Add PLL clock inputs from PLL clock generator. >> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> >> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> >> --- >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- >> 1 file changed, 18 insertions(+), 2 deletions(-) > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > 'i2stx_bclk_ext' was expected > 'i2stx_lrck_ext' was expected > 'i2srx_bclk_ext' was expected > 'i2srx_lrck_ext' was expected > 'tdm_ext' was expected > 'mclk_ext' was expected > 'pll0_out' was expected > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > 'i2stx_bclk_ext' was expected > 'i2stx_lrck_ext' was expected > 'i2srx_bclk_ext' was expected > 'i2srx_lrck_ext' was expected > 'tdm_ext' was expected > 'mclk_ext' was expected > 'pll0_out' was expected > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > > This binding change is incompatible with the existing devicetrees for > the visionfive 2. This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. Best regards, Xingyu Wu
