This patch serises are to add PLL clocks driver and providers by writing and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add documentation and nodes to describe StarFive System Controller(syscon) Registers. This patch serises are based on Linux 6.4-rc1. PLL are high speed, low jitter frequency synthesizers in JH7110. Each PLL clocks work in integer mode or fraction mode by some dividers, and the dividers are set in several syscon registers. The formula for calculating frequency is: Fvco = Fref * (NI + NF) / M / Q1 The first patch adds docunmentation to describe PLL clock bindings, and the second patch adds driver to support PLL clocks for JH7110. The patch 3 modifies the SYSCRG dibindings and adds PLL clock inputs. The patch 4 modifies the system clock driver and changes PLL clock source from PLL clock controller instead of the fixed factor clocks. The patch 5 adds documentation to decribe syscon registers. And the patch 6 adds the stg/sys/aon syscon nodes for JH7110 SoC. The last patch adds PLL clock node and modifies the syscrg node in JH7110 dts file. Changes since v3: - Rebased on Linux 6.4-rc1. - Dropped the 'power-controller' property and used 'power-domain-cells' instead in syscon binding. - Used the data by of_device_id to get the syscon registers' configuration include offset, mask and shift. v3: https://lore.kernel.org/all/20230414024157.53203-1-xingyu.wu@xxxxxxxxxxxxxxxx/ Changes since v2: - Rebased on latest JH7110 basic clock drivers. - Added the complete documentation to describe syscon register. - Added syscon node in JH7110 dts file. - Modified the clock rate selection to match the closest rate in PLL driver when setting rate. v2: https://lore.kernel.org/all/20230316030514.137427-1-xingyu.wu@xxxxxxxxxxxxxxxx/ Changes since v1: - Changed PLL clock node to be child of syscon node in dts. - Modifed the definitions and names of function in PLL clock driver. - Added commit to update syscon and syscrg dt-bindings. v1: https://lore.kernel.org/all/20230221141147.303642-1-xingyu.wu@xxxxxxxxxxxxxxxx/ William Qiu (2): dt-bindings: soc: starfive: Add StarFive syscon module riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu (5): dt-bindings: clock: Add StarFive JH7110 PLL clock generator clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs clk: starfive: jh7110-sys: Modify PLL clocks source riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++ .../clock/starfive,jh7110-syscrg.yaml | 20 +- .../soc/starfive/starfive,jh7110-syscon.yaml | 67 ++++ MAINTAINERS | 13 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 30 +- drivers/clk/starfive/Kconfig | 9 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jh7110-pll.c | 309 ++++++++++++++++ .../clk/starfive/clk-starfive-jh7110-pll.h | 331 ++++++++++++++++++ .../clk/starfive/clk-starfive-jh7110-sys.c | 31 +- .../dt-bindings/clock/starfive,jh7110-crg.h | 6 + 11 files changed, 834 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h base-commit: ac9a78681b921877518763ba0e89202254349d1b -- 2.25.1
