From: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx> The axiethernet driver will use dmaengine framework to communicate with dma controller IP instead of built-in dma programming sequence. To request dma transmit and receive channels the axiethernet driver uses generic dmas, dma-names properties. Also to support the backward compatibility, use "dmas" property to identify as it should use dmaengine framework or legacy driver(built-in dma programming). At this point it is recommended to use dmaengine framework but it's optional. Once the solution is stable will make dmas as required properties. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx> Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@xxxxxxx> --- These changes are on top of below txt to yaml conversion discussion https://lore.kernel.org/all/20230308061223.1358637-1-sarath.babu.naidu.gaddam@xxxxxxx/#Z2e.:20230308061223.1358637-1-sarath.babu.naidu.gaddam::40amd.com:1bindings:net:xlnx::2caxi-ethernet.yaml Changes in V3: 1) Reverted reg and interrupts property to support backward compatibility. 2) Moved dmas and dma-names properties from Required properties. Changes in V2: - None. --- .../devicetree/bindings/net/xlnx,axi-ethernet.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml index 80843c177029..9dfa1976e260 100644 --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml @@ -122,6 +122,16 @@ properties: modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists. + dmas: + items: + - description: TX DMA Channel phandle and DMA request line number + - description: RX DMA Channel phandle and DMA request line number + + dma-names: + items: + - const: tx_chan0 + - const: rx_chan0 + required: - compatible - interrupts @@ -157,6 +167,8 @@ examples: clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; phy-mode = "mii"; reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>; + dmas = <&xilinx_dma 0>, <&xilinx_dma 1>; + dma-names = "tx_chan0", "rx_chan0"; xlnx,rxcsum = <0x2>; xlnx,rxmem = <0x800>; xlnx,txcsum = <0x2>; -- 2.25.1
