On 27.04.2023 23:08:57, Marc Kleine-Budde wrote: > On 27.04.2023 22:45:35, Dario Binacchi wrote: > > > > The series adds support for managing bxCAN controllers in single peripheral > > configuration. > > Unlike stm32f4 SOCs, where bxCAN controllers are only in dual peripheral > > configuration, stm32f7 SOCs contain three CAN peripherals, CAN1 and CAN2 > > in dual peripheral configuration and CAN3 in single peripheral > > configuration: > > - Dual CAN peripheral configuration: > > * CAN1: Primary bxCAN for managing the communication between a secondary > > bxCAN and the 512-byte SRAM memory. > > * CAN2: Secondary bxCAN with no direct access to the SRAM memory. > > This means that the two bxCAN cells share the 512-byte SRAM memory and > > CAN2 can't be used without enabling CAN1. > > - Single CAN peripheral configuration: > > * CAN3: Primary bxCAN with dedicated Memory Access Controller unit and > > 512-byte SRAM memory. > > This really looks good! Great work! Who takes the DT changes? I can take > the whole series. I've upstreamed the DT changes for the first bxCAN driver, so I'll take them this time, too. Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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