Hi Serge,
> From: Serge Semin, Sent: Tuesday, May 2, 2023 4:58 AM
>
> On Wed, Apr 26, 2023 at 01:55:47PM +0900, Yoshihiro Shimoda wrote:
> > Add dw_pcie_link_set_max_cap_width() to set PCI_EXP_LNKCAP_MLW.
> > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > field there is another one which needs to be updated. It's
> > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > the very least the maximum link-width capability CSR won't expose
> > the actual maximum capability.
> >
> > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.60a, March 2015, p.1032
> > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.70a, March 2016, p.1065
> > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.90a, March 2016, p.1057
> > ...
> > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > Version 5.40a, March 2019, p.1396
> > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 5.40a, March 2019, p.1266
> >
> > The commit description is suggested by Serge Semin.
> >
> > Suggested-by: Serge Semin <fancer.lancer@xxxxxxxxx>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index f8926d5ec422..bdc5ebd7cd5f 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -737,6 +737,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
> > }
> >
>
> > +static void dw_pcie_link_set_max_cap_width(struct dw_pcie *pci, int num_lanes)
> > +{
> > + u32 val;
> > + u8 cap;
> > +
> > + if (!num_lanes)
> > + return;
> > +
> > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > + val = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > + val &= ~PCI_EXP_LNKCAP_MLW;
> > + val |= num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT;
> > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, val);
> > +}
>
> Just move the function body to dw_pcie_link_set_max_link_width() thus
> the later method will be as coherent as possible.
I got it.
> Also note the duplicated code can be dropped from the pcie-tegra194.c
> driver. Please submit an additional cleanup patch so the Tegra driver
> author would have it reviewed.
I got it. I'll make such a patch.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> > +
> > static void dw_pcie_link_set_max_width(struct dw_pcie *pci, u32 num_lanes)
> > {
> > u32 val;
> > @@ -1074,6 +1089,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
> > }
> >
> > + dw_pcie_link_set_max_cap_width(pci, pci->num_lanes);
> > dw_pcie_link_set_max_width(pci, pci->num_lanes);
> > dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> > }
> > --
> > 2.25.1
> >
