On Wed, Apr 26, 2023 at 11:58 AM Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> wrote: > > Introduce PLL clock controller for Amlogic A1 SoC family. > The clock unit is an APB slave module that is designed for generating all > of the internal and system clocks. > The SoC uses an external 24MHz crystal; there are 4 internal PLLs: > SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources. > > Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx> > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
