On Thu, Apr 20, 2023 at 5:45 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@xxxxxxxxxxxxx> wrote:
>
> On Cherry boards, the IP at 0x1c015000 (dp_intf0) is used as primary
> dp-intf, while the other at 0x1c113000 (dp_intf1) is used as secondary:
> assign them to dp-intf{0,1} aliases respectively.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++
This should be applied at the SoC level. The display pipeline is fixed in
MMSYS, so it applies to all MT8195 devices.
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 0820e9ba3829..918380697a9a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -10,6 +10,8 @@
>
> / {
> aliases {
> + dp-intf0 = &dp_intf0;
> + dp-intf1 = &dp_intf1;
> i2c0 = &i2c0;
> i2c1 = &i2c1;
> i2c2 = &i2c2;
> --
> 2.40.0
>
>
