Hello Christophe,
On Sat, Apr 15, 2023 at 02:16:09PM +0200, Christophe JAILLET wrote:
> Le 15/04/2023 à 13:13, Jonathan Neuschäfer a écrit :
> > This driver implements the following features w.r.t. the clock and reset
> > controller in the WPCM450 SoC:
> >
> > - It calculates the rates for all clocks managed by the clock controller
> > - It leaves the clock tree mostly unchanged, except that it enables/
> > disables clock gates based on usage.
> > - It exposes the reset lines managed by the controller using the
> > Generic Reset Controller subsystem
> >
> > NOTE: If the driver and the corresponding devicetree node are present,
> > the driver will disable "unused" clocks. This is problem until
> > the clock relations are properly declared in the devicetree (in a
> > later patch). Until then, the clk_ignore_unused kernel parameter
> > can be used as a workaround.
> >
> > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer-hi6Y0CQ0nG0@xxxxxxxxxxxxxxxx>
> > ---
[...]
> > + // Enables/gates
> > + for (i = 0; i < ARRAY_SIZE(clken_data); i++) {
> > + const struct wpcm450_clken_data *data = &clken_data[i];
> > +
> > + hw = clk_hw_register_gate_parent_data(NULL, data->name, &data->parent, data->flags,
> > + clk_base + REG_CLKEN, data->bitnum,
> > + data->flags, &wpcm450_clk_lock);
>
> If an error occures in the 'for' loop or after it, should this be
> clk_hw_unregister_gate()'ed somewhere?
Ideally yes —
in this case, if the clock driver fails, the system is arguably in such
a bad state that there isn't much point in bothering.
>
> CJ
>
> > + if (IS_ERR(hw)) {
> > + pr_err("Failed to register gate: %pe\n", hw);
> > + goto err_free;
> > + }
> > + clk_data->hws[data->bitnum] = hw;
> > + }
Best regards,
Jonathan
Attachment:
signature.asc
Description: PGP signature
