> On Fri, Mar 31, 2023 at 03:12:36PM +0200, Lorenzo Bianconi wrote: > > Since cpuboot, ilm and dlm memory region are not part of MT7986 SoC RAM, > > That's not really a requirement. Is that the only "problem" here? I would say this series allows to be closer to a standard binding and at the same time helps with uboot compatibility. > > Certainly going from a standard binding to a custom phandle reference is > not an improvement. > > > move them in dedicated mt7986a syscon dts nodes. > > What makes them a syscon? Are they memory or h/w registers? Can't be > both... > > Perhaps mmio-sram? ilm and dlm do not have h/w registers afaik, they are chip memory used to store firmware information, syscon is just the closest binding I found. I did not find mmio-sram, my fault. Regards, Lorenzo > > > At the same time we keep backward-compatibility with older dts version where > > cpuboot, ilm and dlm were defined as reserved-memory child nodes. > > Doesn't really seem big enough issue to justify carrying this. > > Rob
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