On Wed, Apr 05, 2023, Krishna Kurapati wrote: > Currently the DWC3 driver supports only single port controller which > requires at most two PHYs ie HS and SS PHYs. There are SoCs that has > DWC3 controller with multiple ports that can operate in host mode. > Some of the port supports both SS+HS and other port supports only HS > mode. > > This change primarily refactors the Phy logic in core driver to allow > multiport support with Generic Phy's. > > Chananges have been tested on QCOM SoC SA8295P which has 4 ports (2 > are HS+SS capable and 2 are HS only capable). > > Changes in v6: > Updated comments in code after. > Updated variables names appropriately as per review comments. > Updated commit text in patch-2 and added additional info as per review > comments. > The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected > it in this version. > > Changes in v5: > Added DT support for first port of Teritiary USB controller on SA8540-Ride > Added support for reading port info from XHCI Extended Params registers. > > Changes in RFC v4: > Added DT support for SA8295p. > > Changes in RFC v3: > Incase any PHY init fails, then clear/exit the PHYs that > are already initialized. > > Changes in RFC v2: > Changed dwc3_count_phys to return the number of PHY Phandles in the node. > This will be used now in dwc3_extract_num_phys to increment num_usb2_phy > and num_usb3_phy. > > Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its > structure such that the first half is for HS-PHY and second half is for > SS-PHY. > > In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is > present, pass proper SS_IDX else pass -1. > > Link to v5: https://urldefense.com/v3/__https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@xxxxxxxxxxx/__;!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O7oBPDywQ$ > Link to RFC v4: https://urldefense.com/v3/__https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@xxxxxxxxxxx/__;!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5p58Ga7A$ > Link to RFC v3: https://urldefense.com/v3/__https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@xxxxxxxxxxx/*r__;Iw!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5eLTSOZg$ > Link to RFC v2: https://urldefense.com/v3/__https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@xxxxxxxxxxx/*r__;Iw!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5CAsP83Q$ > > Krishna Kurapati (8): > dt-bindings: usb: Add bindings for multiport properties on DWC3 > controller > usb: dwc3: core: Access XHCI address space temporarily to read port > info > usb: dwc3: core: Skip setting event buffers for host only controllers > usb: dwc3: core: Refactor PHY logic to support Multiport Controller > usb: dwc3: qcom: Add multiport controller support for qcom wrapper > arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 > arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB > ports > arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb > controller > > .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ > drivers/usb/dwc3/core.c | 373 ++++++++++++++---- > drivers/usb/dwc3/core.h | 71 +++- > drivers/usb/dwc3/drd.c | 13 +- > drivers/usb/dwc3/dwc3-qcom.c | 28 +- > 8 files changed, 523 insertions(+), 102 deletions(-) > > -- > 2.40.0 > Please check if your patches and mailing client. Looks like they are corrupted. Thanks, Thinh
