Add support for UFS ICE by adding the qcom,ice property and the ICE dedicated devicetree node. While at it, add the reg-name property to the UFS HC node to be in line with older platforms. Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> --- The v4 is here: https://lore.kernel.org/all/20230327134734.3256974-8-abel.vesa@xxxxxxxxxx/ Changes since v4: * none Changes since v3: * none arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index c6613654942a..dcfbbf33663a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1889,6 +1889,7 @@ ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sm8550-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; + reg-names = "std"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; @@ -1932,9 +1933,18 @@ ufs_mem_hc: ufs@1d84000 { <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,sm8550-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; -- 2.34.1
