Hey Hal, On Sat, Apr 01, 2023 at 07:19:12PM +0800, Hal Feng wrote: > This patch series adds basic clock, reset & DT support for StarFive > JH7110 SoC. > > @Stephen and @Conor, I have made this series start with the shared > dt-bindings, so it will be easier to merge. Thanks. I probably should have asked for that, makes my life easier that's for sure! > @Conor, patch 1, 2, 16~21 were already in your branch. Patch 22 is the > same with the patch [1] I submitted before, which you had accepted but > not merge it into your branch. I hadn't merged that into anywhere, so I just went and dropped the original incarnation of that branch and have re-created it. I don't recall there being a maintainers pattern error (from running scripts/get_maintainer.pl --self-test=patterns) with what I had done in my branch, but with your patch 1 applied I see one. To save myself a complaint from LKP, I stripped out the MAINTAINERS bits from patch 1 into their own patch that can go with the clock/reset bits. I squashed 22 into "riscv: dts: starfive: Add initial StarFive JH7110 device tree" since there's no reason to add something knowingly incorrect IMO. I've gone and pushed out the following as riscv-jh7110_initial_dts: riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device riscv: dts: starfive: Add StarFive JH7110 pin function definitions riscv: dts: starfive: Add initial StarFive JH7110 device tree dt-bindings: riscv: Add SiFive S7 compatible dt-bindings: interrupt-controller: Add StarFive JH7110 plic dt-bindings: timer: Add StarFive JH7110 clint dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator dt-bindings: clock: Add StarFive JH7110 system clock and reset generator And the rest as riscv-jh7110_clk_reset: MAINTAINERS: generalise StarFive clk/reset entries reset: starfive: Add StarFive JH7110 reset driver clk: starfive: Add StarFive JH7110 always-on clock driver clk: starfive: Add StarFive JH7110 system clock driver reset: starfive: jh71x0: Use 32bit I/O on 32bit registers reset: starfive: Rename "jh7100" to "jh71x0" for the common code reset: starfive: Extract the common JH71X0 reset code reset: starfive: Factor out common JH71X0 reset code reset: Create subdirectory for StarFive drivers reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE clk: starfive: Rename "jh7100" to "jh71x0" for the common code clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h clk: starfive: Factor out common JH7100 and JH7110 code clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator dt-bindings: clock: Add StarFive JH7110 system clock and reset generator <https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/refs> As it looks like everything has been resolved in terms of comments on v6, provided LKP doesn't complain or people don't spot something else, my plan is to send Stephen a PR around Wednesday for the driver bits. Please LMK if I screwed up anything, Conor.
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