On 17.03.2023 07:53, Rohit Agarwal wrote:
> Add support for PCIe Endpoint controller on the
> Qualcomm SDX65 platform.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 084daf8..a7d8ad9 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/gpio/gpio.h>
This should be sorted alphabetically
Other than that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
>
> / {
> #address-cells = <1>;
> @@ -293,6 +294,56 @@
> status = "disabled";
> };
>
> + pcie_ep: pcie-ep@1c00000 {
> + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
> + reg = <0x01c00000 0x3000>,
> + <0x40000000 0xf1d>,
> + <0x40000f20 0xa8>,
> + <0x40001000 0x1000>,
> + <0x40200000 0x100000>,
> + <0x01c03000 0x3000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "addr_space",
> + "mmio";
> +
> + qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> +
> + clocks = <&gcc GCC_PCIE_AUX_CLK>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_PCIE_SLEEP_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "sleep",
> + "ref";
> +
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "global", "doorbell";
> +
> + resets = <&gcc GCC_PCIE_BCR>;
> + reset-names = "core";
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + phys = <&pcie_phy>;
> + phy-names = "pcie-phy";
> +
> + max-link-speed = <3>;
> + num-lanes = <2>;
> +
> + status = "disabled";
> + };
> +
> pcie_phy: phy@1c06000 {
> compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> reg = <0x01c06000 0x2000>;
> @@ -330,6 +381,11 @@
> #hwlock-cells = <1>;
> };
>
> + tcsr: syscon@1fcb000 {
> + compatible = "qcom,sdx65-tcsr", "syscon";
> + reg = <0x01fc0000 0x1000>;
> + };
> +
> remoteproc_mpss: remoteproc@4080000 {
> compatible = "qcom,sdx55-mpss-pas";
> reg = <0x04080000 0x4040>;
