On 17.03.2023 07:53, Rohit Agarwal wrote:
> Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
> used by the PCIe EP controller.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 192f9f9..084daf8 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -293,6 +293,37 @@
> status = "disabled";
> };
>
> + pcie_phy: phy@1c06000 {
> + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> + reg = <0x01c06000 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_EN>,
> + <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
> + <&gcc GCC_PCIE_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
> + "pipe";
> +
> + resets = <&gcc GCC_PCIE_PHY_BCR>;
> + reset-names = "phy";
> +
> + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x01f40000 0x40000>;
