> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > Sent: Tuesday, March 14, 2023 9:22 PM > To: Gaddam, Sarath Babu Naidu > <sarath.babu.naidu.gaddam@xxxxxxx>; davem@xxxxxxxxxxxxx; > edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx; pabeni@xxxxxxxxxx; > robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx > Cc: michal.simek@xxxxxxxxxx; radhey.shyam.pandey@xxxxxxxxxx; > netdev@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-arm- > kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Sarangi, > Anirudha <anirudha.sarangi@xxxxxxx>; Katakam, Harini > <harini.katakam@xxxxxxx>; git (AMD-Xilinx) <git@xxxxxxx> > Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet: > convert bindings document to yaml > > On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote: > > From: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx> > > > > Convert the bindings document for Xilinx AXI Ethernet Subsystem from > > txt to yaml. No changes to existing binding description. > > > > (...) > > > +properties: > > + compatible: > > + enum: > > + - xlnx,axi-ethernet-1.00.a > > + - xlnx,axi-ethernet-1.01.a > > + - xlnx,axi-ethernet-2.01.a > > + > > + reg: > > + description: > > + Address and length of the IO space, as well as the address > > + and length of the AXI DMA controller IO space, unless > > + axistream-connected is specified, in which case the reg > > + attribute of the node referenced by it is used. > > Did you test it with axistream-connected? The schema and description > feel contradictory and tests would point the issue. Thanks for review comments. We tested with axistream-connected and did not observe any errors. Do you anticipate any issues/errors ? will address remaining review comments. Thanks, sarath > > + maxItems: 2 > > + > > + interrupts: > > + items: > > + - description: Ethernet core interrupt > > + - description: Tx DMA interrupt > > + - description: Rx DMA interrupt > > + description: > > + Ethernet core interrupt is optional. If axistream-connected > property is > > + present DMA node should contains TX/RX DMA interrupts else > DMA interrupt > > + resources are mentioned on ethernet node. > > + minItems: 1 > > + > > + phy-handle: true > > + > > + xlnx,rxmem: > > + description: > > + Set to allocated memory buffer for Rx/Tx in the hardware. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + phy-mode: > > + items: > > + - description: MII > > + - description: GMII > > + - description: RGMII > > + - description: SGMII > > + - description: 1000BaseX > > I have doubts you tested it... Since when this is a list? How does it exactly > work and what do you want to show here? > > connection type is enum. > > > > + minItems: 1 > > + > > + xlnx,phy-type: > > + description: > > + Do not use, but still accepted in preference to phy-mode. > > + deprecated: true > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + xlnx,txcsum: > > + description: > > + TX checksum offload. 0 or empty for disabling TX checksum > offload, > > + 1 to enable partial TX checksum offload and 2 to enable full TX > > + checksum offload. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [0, 1, 2] > > + > > + xlnx,rxcsum: > > + description: > > + RX checksum offload. 0 or empty for disabling RX checksum > offload, > > + 1 to enable partial RX checksum offload and 2 to enable full RX > > + checksum offload. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [0, 1, 2] > > + > > + xlnx,switch-x-sgmii: > > + type: boolean > > + description: > > + Indicate the Ethernet core is configured to support both 1000BaseX > and > > + SGMII modes. If set, the phy-mode should be set to match the > mode > > + selected on core reset (i.e. by the basex_or_sgmii core input line). > > + > > + clocks: > > + items: > > + - description: Clock for AXI register slave interface. > > + - description: AXI4-Stream clock for TXD RXD TXC and RXS > interfaces. > > + - description: Ethernet reference clock, used by signal delay > primitives > > + and transceivers. > > + - description: MGT reference clock (used by optional internal > > + PCS/PMA PHY) > > + > > + clock-names: > > + items: > > + - const: s_axi_lite_clk > > + - const: axis_clk > > + - const: ref_clk > > + - const: mgt_clk > > + > > + axistream-connected: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: Phandle of AXI DMA controller which contains the > resources > > + used by this device. If this is specified, the DMA-related resources > > + from that device (DMA registers and DMA TX/RX interrupts) rather > than > > + this one will be used. > > + > > + mdio: > > + type: object > > + > > + pcs-handle: > > maxItems: 1 > > > + description: Phandle to the internal PCS/PMA PHY in SGMII or > 1000Base-X > > + modes, where "pcs-handle" should be used to point to the > PCS/PMA PHY, > > + and "phy-handle" should point to an external PHY if exists. > > Best regards, > Krzysztof
