Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx> Reviewed-by: Rob Herring <robh@xxxxxxxxxx> --- Changes in v9: - Replace master/slave terms with primary/secondary. Changes in v5: - Add Rob Herring's Reviewed-by tag. Changes in v4: - Remove "st,stm32f4-bxcan-core" compatible. In this way the can nodes (compatible "st,stm32f4-bxcan") are no longer children of a parent node with compatible "st,stm32f4-bxcan-core". - Add the "st,gcan" property (global can memory) to can nodes which references a "syscon" node containing the shared clock and memory addresses. Changes in v3: - Remove 'Dario Binacchi <dariobin@xxxxxxxxx>' SOB. - Add description to the parent of the two child nodes. - Move "patterProperties:" after "properties: in top level before "required". - Add "clocks" to the "required:" list of the child nodes. Changes in v2: - Change the file name into 'st,stm32-bxcan-core.yaml'. - Rename compatibles: - st,stm32-bxcan-core -> st,stm32f4-bxcan-core - st,stm32-bxcan -> st,stm32f4-bxcan - Rename master property to st,can-master. - Remove the status property from the example. - Put the node child properties as required. .../bindings/net/can/st,stm32-bxcan.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml new file mode 100644 index 000000000000..ca97ba3c2b05 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics bxCAN controller + +description: STMicroelectronics BxCAN controller for CAN bus + +maintainers: + - Dario Binacchi <dario.binacchi@xxxxxxxxxxxxxxxxxxxx> + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + enum: + - st,stm32f4-bxcan + + st,can-primary: + description: + Primary and secondary mode of the bxCAN peripheral is only relevant + if the chip has two CAN peripherals. In that case they share some + of the required logic. + Note: The ST documentation uses master/slave terms instead of + primary/secondary. + type: boolean + + reg: + maxItems: 1 + + interrupts: + items: + - description: transmit interrupt + - description: FIFO 0 receive interrupt + - description: FIFO 1 receive interrupt + - description: status change error interrupt + + interrupt-names: + items: + - const: tx + - const: rx0 + - const: rx1 + - const: sce + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + st,gcan: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + The phandle to the gcan node which allows to access the 512-bytes + SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2 + secondary) in dual CAN peripheral configuration. + +required: + - compatible + - reg + - interrupts + - resets + - clocks + - st,gcan + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/stm32fx-clock.h> + #include <dt-bindings/mfd/stm32f4-rcc.h> + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + }; -- 2.32.0
