Hi Vaishnav, Thanks for the series. On Mar 14, 2023 at 17:25:13 +0530, Vaishnav Achath wrote: > From: Pratyush Yadav <p.yadav@xxxxxx> > > TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate > capture over a CSI-2 bus. > > The Cadence CSI2RX IP acts as a bridge between the TI specific parts and > the CSI-2 protocol parts. TI then has a wrapper on top of this bridge > called the SHIM layer. It takes in data from stream 0, repacks it, and > sends it to memory over PSI-L DMA. > > This driver acts as the "front end" to V4L2 client applications. It > implements the required ioctls and buffer operations, passes the > necessary calls on to the bridge, programs the SHIM layer, and performs > DMA via the dmaengine API to finally return the data to a buffer > supplied by the application. > > Signed-off-by: Pratyush Yadav <p.yadav@xxxxxx> > Signed-off-by: Jai Luthra <j-luthra@xxxxxx> > Signed-off-by: Vaishnav Achath <vaishnav.a@xxxxxx> > --- [...] > diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c > b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c > new file mode 100644 > index 000000000000..0c8dad049f5b > --- /dev/null > +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c > @@ -0,0 +1,1022 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * TI CSI2 RX driver. > + * > + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ > + * > + * Author: Pratyush Yadav <p.yadav@xxxxxx> > + */ > + > +#include <linux/bitfield.h> > +#include <linux/dmaengine.h> > +#include <linux/module.h> > +#include <linux/of_platform.h> > +#include <linux/platform_device.h> > + > +#include <media/mipi-csi2.h> > +#include <media/v4l2-device.h> > +#include <media/v4l2-ioctl.h> > +#include <media/videobuf2-dma-contig.h> > + > +#define TI_CSI2RX_MODULE_NAME "j721e-csi2rx" > + > +#define SHIM_CNTL 0x10 > +#define SHIM_CNTL_PIX_RST BIT(0) > + > +#define SHIM_DMACNTX 0x20 > +#define SHIM_DMACNTX_EN BIT(31) > +#define SHIM_DMACNTX_YUV422 GENMASK(27, 26) > +#define SHIM_DMACNTX_FMT GENMASK(5, 0) > +#define SHIM_DMACNTX_UYVY 0 > +#define SHIM_DMACNTX_VYUY 1 > +#define SHIM_DMACNTX_YUYV 2 > +#define SHIM_DMACNTX_YVYU 3 > + > +#define SHIM_PSI_CFG0 0x24 > +#define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0) > +#define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 15) This should be GENMASK(31, 16) instead. > + > +#define PSIL_WORD_SIZE_BYTES 16 > +/* [...] Thanks, Jai
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