Hi Vasily, On Thu, Mar 16, 2023 at 8:16 AM Vasily Khoruzhick <anarsoul@xxxxxxxxx> wrote: > > On Wed, Mar 15, 2023 at 9:02 AM Tianling Shen <cnsztl@xxxxxxxxx> wrote: > > > > - Changed phy-mode to rgmii. > > > > - Fixed pull type in pinctrl for gmac0. > > > > - Removed duplicate properties in mdio node. > > These properties are defined in the gmac0 node already. > > > > Signed-off-by: Tianling Shen <cnsztl@xxxxxxxxx> > > --- > > arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++----- > > 1 file changed, 2 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts > > index e9adf5e66529..2a1118f15c29 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts > > @@ -57,7 +57,7 @@ > > assigned-clock-rates = <0>, <125000000>; > > clock_in_out = "output"; > > phy-handle = <&rgmii_phy0>; > > - phy-mode = "rgmii-id"; > > + phy-mode = "rgmii"; > > pinctrl-names = "default"; > > pinctrl-0 = <&gmac0_miim > > &gmac0_tx_bus2 > > @@ -79,9 +79,6 @@ > > reg = <1>; > > pinctrl-0 = <ð_phy0_reset_pin>; > > pinctrl-names = "default"; > > - reset-assert-us = <10000>; > > - reset-deassert-us = <50000>; > > - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; > > Hmm, I don't see RK_PC4 being used anywhere else. gmac0 has RK_PC5 as Yes, it's a typo, it should be RK_RC5. > snsp,reset-gpio. So it essentially drops reset for the PHY. Is it > expected? snsp,reset-gpio defined reset already, so we don't need to set it here again. --- snsp,reset-gpio is the legacy binding, but I still have no idea why reset-gpios doesn't work, the dwmac driver will fail to lookup phy: [ 10.398514] rk_gmac-dwmac fe2a0000.ethernet eth0: no phy found [ 10.399061] rk_gmac-dwmac fe2a0000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) Any ideas would be appreciated. Thanks, Tianling. > > > }; > > }; > > > > @@ -115,7 +112,7 @@ > > &pinctrl { > > gmac0 { > > eth_phy0_reset_pin: eth-phy0-reset-pin { > > - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; > > + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; > > }; > > }; > > > > -- > > 2.17.1 > >