From: Elad Nachman <enachman@xxxxxxxxxxx>
Add support for AC5 SoC with MSI and in message emulated INTx mode.
There are differences in the registers addresses, blocks, DDR location
for coherent DMA allocation and additional implementation specific registers.
In addition, support cases of older Designware IP (Armada 7020) which supports
above 4GB PCIe physical memory window by use of device tree.
v4:
1) Fix commit subject / messages formatting and naming
2) Remove empty lines removal / addition
3) Split patch number five from series to two patches
4) Replace added dt-binding for DMA mask with dma-ranges
v3:
1) Add dt bindings for DMA and region mask bits
2) Support AC5 Legacy PCIe interrupts
3) Introduce Configurable DMA mask
4) Introduce region limit from DT
v2:
1) add patch with adding compatible string for dt-bindings description
2) fix W1 warnings which caused by unused leftover code
3) Use one xlate function to translate ac5 dbi access. Also add
mode description in comments about this translation.
4) Use correct name of Raz
5) Use matching data to pass the SoC specific params (type & ops)
Elad Nachman (5):
dt-bindings: PCI: dwc: Add dma-ranges, region mask
PCI: armada8k: support AC5 INTx PCIe interrupts
PCI: armada8k: support reg regions according to DT.
PCI: dwc: Introduce configurable DMA mask
PCI: dwc: Introduce region limit from DT
Raz Adashi (1):
PCI: armada8k: Add AC5 SoC support
Vadym Kochan (1):
dt-bindings: PCI: armada8k: Add compatible string for AC5 SoC
Yuval Shaia (1):
PCI: armada8k: Add AC5 MSI support
.../devicetree/bindings/pci/pci-armada8k.txt | 4 +-
.../bindings/pci/snps,dw-pcie-common.yaml | 5 +
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 6 +
drivers/pci/controller/dwc/pcie-armada8k.c | 184 +++++++++++++++---
.../pci/controller/dwc/pcie-designware-host.c | 28 ++-
drivers/pci/controller/dwc/pcie-designware.c | 12 +-
6 files changed, 206 insertions(+), 33 deletions(-)
--
2.17.1
