On Mon, Mar 06, 2023 at 02:15:25PM -0500, Sean Anderson wrote: > This is a generic binding for simple MMIO GPIO controllers. Although we > have a single driver for these controllers, they were previously spread > over several files. Consolidate them. The register descriptions are > adapted from the comments in the source. There is no set order for the > registers, so I have not specified one. > > Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx> > --- > > Changes in v10: > - New > > .../bindings/gpio/brcm,bcm6345-gpio.yaml | 16 +-- > .../devicetree/bindings/gpio/gpio-mmio.yaml | 136 ++++++++++++++++++ > .../bindings/gpio/ni,169445-nand-gpio.txt | 38 ----- > .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 ----- > 4 files changed, 137 insertions(+), 91 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > delete mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > > diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > index 4d69f79df859..e11f4af49c52 100644 > --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml > @@ -4,7 +4,7 @@ > $id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Broadcom BCM6345 GPIO controller > +title: Broadcom BCM63xx GPIO controller > > maintainers: > - Álvaro Fernández Rojas <noltari@xxxxxxxxx> > @@ -18,8 +18,6 @@ description: |+ > > BCM6338 have 8-bit data and dirout registers, where GPIO state can be read > and/or written, and the direction changed from input to output. > - BCM6345 have 16-bit data and dirout registers, where GPIO state can be read > - and/or written, and the direction changed from input to output. > BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data > and dirout registers, where GPIO state can be read and/or written, and the > direction changed from input to output. > @@ -29,7 +27,6 @@ properties: > enum: > - brcm,bcm6318-gpio > - brcm,bcm6328-gpio > - - brcm,bcm6345-gpio > - brcm,bcm6358-gpio > - brcm,bcm6362-gpio > - brcm,bcm6368-gpio > @@ -63,17 +60,6 @@ required: > additionalProperties: false > > examples: > - - | > - gpio@fffe0406 { > - compatible = "brcm,bcm6345-gpio"; > - reg-names = "dirout", "dat"; > - reg = <0xfffe0406 2>, <0xfffe040a 2>; > - native-endian; > - > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - | > gpio@0 { > compatible = "brcm,bcm63268-gpio"; > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > new file mode 100644 > index 000000000000..fd5c7055d542 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml > @@ -0,0 +1,136 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Generic MMIO GPIO > + > +maintainers: > + - Linus Walleij <linus.walleij@xxxxxxxxxx> > + - Bartosz Golaszewski <brgl@xxxxxxxx> > + > +description: | Don't need '|' unless you want line endings preserved. Elsewhere too. > + Some simple GPIO controllers may consist of a single data register or a pair > + of set/clear-bit registers. Such controllers are common for glue logic in > + FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped > + NAND-style parallel busses. > + > +properties: > + big-endian: > + true big-endian: true > + > + compatible: > + enum: > + - brcm,bcm6345-gpio # Broadcom BCM6345 GPIO controller > + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller > + - ni,169445-nand-gpio # National Instruments 169445 GPIO NAND controller > + > + '#gpio-cells': > + const: 2 > + > + gpio-controller: > + true ditto. > + > + reg: > + minItems: 1 > + description: | > + A list of registers in the controller. The width of each register is > + determined by its size. All registers must have the same width. The number > + of GPIOs is set by the width, with bit 0 corresponding to GPIO 0. > + items: > + - description: | > + Register to READ the value of the GPIO lines. If GPIO line is high, > + the bit will be set. If the GPIO line is low, the bit will be cleared. > + This register may also be used to drive GPIOs if the SET register is > + omitted. > + - description: | > + Register to SET the value of the GPIO lines. Setting a bit in this > + register will drive the GPIO line high. > + - description: | > + Register to CLEAR the value of the GPIO lines. Setting a bit in this > + register will drive the GPIO line low. If this register is omitted, > + the SET register will be used to clear the GPIO lines as well, by > + actively writing the line with 0. > + - description: | > + Register to set the line as OUTPUT. Setting a bit in this register > + will turn that line into an output line. Conversely, clearing a bit > + will turn that line into an input. > + - description: | > + Register to set this line as INPUT. Setting a bit in this register > + will turn that line into an input line. Conversely, clearing a bit > + will turn that line into an output. > + > + reg-names: > + minItems: 1 > + maxItems: 5 > + items: > + enum: > + - dat > + - set > + - clr > + - dirout > + - dirin > + > + native-endian: > + true > + > + no-output: > + $ref: /schemas/types.yaml#/definitions/flag > + description: | > + If this property is present, the controller cannot drive the GPIO lines. > + > +required: > + - compatible > + - reg > + - reg-names > + - '#gpio-cells' > + - gpio-controller > + > +additionalProperties: false > + > +examples: > + - | > + nand-gpio-out@1f300010 { Use generic node name: gpio@... > + compatible = "ni,169445-nand-gpio"; > + reg = <0x1f300010 0x4>; > + reg-names = "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + nand-gpio-in@1f300014 { > + compatible = "ni,169445-nand-gpio"; > + reg = <0x1f300014 0x4>; > + reg-names = "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + no-output; > + }; > + > + gpio0@e0000000 { > + compatible = "wd,mbl-gpio"; > + reg-names = "dat"; > + reg = <0xe0000000 0x1>; > + #gpio-cells = <2>; > + gpio-controller; > + }; > + > + gpio1@e0100000 { > + compatible = "wd,mbl-gpio"; > + reg-names = "dat"; > + reg = <0xe0100000 0x1>; > + #gpio-cells = <2>; > + gpio-controller; > + no-output; > + }; > + > + gpio@fffe0406 { > + compatible = "brcm,bcm6345-gpio"; > + reg-names = "dirout", "dat"; > + reg = <0xfffe0406 2>, <0xfffe040a 2>; > + native-endian; > + > + gpio-controller; > + #gpio-cells = <2>; > + }; > diff --git a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > deleted file mode 100644 > index ca2f8c745a27..000000000000 > --- a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt > +++ /dev/null > @@ -1,38 +0,0 @@ > -Bindings for the National Instruments 169445 GPIO NAND controller > - > -The 169445 GPIO NAND controller has two memory mapped GPIO registers, one > -for input (the ready signal) and one for output (control signals). It is > -intended to be used with the GPIO NAND driver. > - > -Required properties: > - - compatible: should be "ni,169445-nand-gpio" > - - reg-names: must contain > - "dat" - data register > - - reg: address + size pairs describing the GPIO register sets; > - order must correspond with the order of entries in reg-names > - - #gpio-cells: must be set to 2. The first cell is the pin number and > - the second cell is used to specify the gpio polarity: > - 0 = active high > - 1 = active low > - - gpio-controller: Marks the device node as a gpio controller. > - > -Optional properties: > - - no-output: disables driving output on the pins > - > -Examples: > - gpio1: nand-gpio-out@1f300010 { > - compatible = "ni,169445-nand-gpio"; > - reg = <0x1f300010 0x4>; > - reg-names = "dat"; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio2: nand-gpio-in@1f300014 { > - compatible = "ni,169445-nand-gpio"; > - reg = <0x1f300014 0x4>; > - reg-names = "dat"; > - gpio-controller; > - #gpio-cells = <2>; > - no-output; > - }; > diff --git a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt b/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > deleted file mode 100644 > index 038c3a6a1f4d..000000000000 > --- a/Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt > +++ /dev/null > @@ -1,38 +0,0 @@ > -Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers. > - > -The Western Digital MyBook Live has two memory-mapped GPIO controllers. > -Both GPIO controller only have a single 8-bit data register, where GPIO > -state can be read and/or written. > - > -Required properties: > - - compatible: should be "wd,mbl-gpio" > - - reg-names: must contain > - "dat" - data register > - - reg: address + size pairs describing the GPIO register sets; > - order must correspond with the order of entries in reg-names > - - #gpio-cells: must be set to 2. The first cell is the pin number and > - the second cell is used to specify the gpio polarity: > - 0 = active high > - 1 = active low > - - gpio-controller: Marks the device node as a gpio controller. > - > -Optional properties: > - - no-output: GPIOs are read-only. > - > -Examples: > - gpio0: gpio0@e0000000 { > - compatible = "wd,mbl-gpio"; > - reg-names = "dat"; > - reg = <0xe0000000 0x1>; > - #gpio-cells = <2>; > - gpio-controller; > - }; > - > - gpio1: gpio1@e0100000 { > - compatible = "wd,mbl-gpio"; > - reg-names = "dat"; > - reg = <0xe0100000 0x1>; > - #gpio-cells = <2>; > - gpio-controller; > - no-output; > - }; > -- > 2.35.1.1320.gc452695387.dirty >
