Add StarFive JH7110 SoC USB 3.0 phy dt-binding. USB controller is cadence USB 3.0 IP. Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx> --- .../bindings/phy/starfive,jh7110-usb-phy.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml new file mode 100644 index 000000000000..05b6c47d4a86 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive USB 2.0 and 3.0 PHY + +maintainers: + - Minda Chen<minda.chen@xxxxxxxxxxxxxxxx> + +properties: + compatible: + items: + - const: starfive,jh7110-usb-phy + + reg: + maxItems: 2 + + reg-names: + items: + - const: usb3 + - const: usb2 + + clocks: + maxItems: 8 + + clock-names: + items: + - const: usb_125m + - const: usb0_app_125 + - const: usb0_lpm + - const: usb0_stb + - const: usb0_apb + - const: usb0_axi + - const: usb0_utmi_apb + + resets: + items: + - description: USB0_PWRUP reset + - description: USB0_APB reset + - description: USB0_AXI reset + - description: USB0_UTMI_APB reset + + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to System Register Controller sys_syscon node. + - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of SYS_SYSCONSAIF__SYSCFG register for USB. + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle to System Register Controller stg_syscon node. + - description: offset of STG_SYSCONSAIF__SYSCFG register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset + for USB. + + dr_mode: + description: PHY mode. + enum: + - host + - peripheral + - otg + + starfive,usb2-only + description: Set USB using usb 2.0 phy. Supprt USB 2.0 only + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset + - starfive,sys-syscon + - starfive,stg-syscon + - dr_mode + - '#phy-cells' + +additionalProperties: false + +examples: + - | + usbphy@10200000 { + compatible = "starfive,jh7110-usb"; + reg = <0x0 0x10210000 0x0 0x1000>, + <0x0 0x10200000 0x0 0x1000>; + reg-names = "usb3", "usb2"; + clocks = <&syscrg 95>, + <&stgcrg 6>, + <&stgcrg 4>, + <&stgcrg 5>, + <&stgcrg 1>, + <&stgcrg 3>, + <&stgcrg 2>; + clock-names = "usb_125m", "usb0_app_125", "usb0_lpm", + "usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb"; + resets = <&stgcrg 10>, + <&stgcrg 8>, + <&stgcrg 7>, + <&stgcrg 9>; + starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>; + starfive,sys-syscon = <&sys_syscon 0x18>; + dr_mode = "host"; + #phy-cells = <0>; + }; -- 2.17.1
