在 2023/3/3 21:45:44, Andrew Lunn 写道:
>> + gmac0: ethernet@16030000 {
>> + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
>> + reg = <0x0 0x16030000 0x0 0x10000>;
>> + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
>> + <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
>> + <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
>> + <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
>> + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
>> + clock-names = "stmmaceth", "pclk", "ptp_ref",
>> + "tx", "gtx";
>> + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
>> + <&aoncrg JH7110_AONRST_GMAC0_AHB>;
>> + reset-names = "stmmaceth", "ahb";
>> + interrupts = <7>, <6>, <5>;
>> + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
>> + phy-mode = "rgmii-id";
>
> phy-mode is a board property, not a SoC property. It should be in the
> board .dts file, not the SoC .dtsi file.
Thanks. I will fix it in the next version.
>
>> + snps,multicast-filter-bins = <64>;
>> + snps,perfect-filter-entries = <8>;
>> + rx-fifo-depth = <2048>;
>> + tx-fifo-depth = <2048>;
>> + snps,fixed-burst;
>> + snps,no-pbl-x8;
>> + snps,force_thresh_dma_mode;
>> + snps,axi-config = <&stmmac_axi_setup>;
>> + snps,tso;
>> + snps,en-tx-lpi-clockgating;
>> + snps,txpbl = <16>;
>> + snps,rxpbl = <16>;
>> + status = "disabled";
>> + phy-handle = <&phy0>;
>
> The PHY is external, so this is also a board property, not a SoC
> property.
Will fix, thanks.
>
>> +
>> + mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "snps,dwmac-mdio";
>> +
>> + phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + };
>
> The PHY is also a board property. You could for example design a board
> where both PHYs are on one MDIO bus, in order to save two SoC pins.
Sounds like a good idea.
>
> Andrew
Thank you for taking the time to review.
--
Best regards,
Samin
