On 18.01.2023 21:48, Bhupesh Sharma wrote:
> On Thu, 19 Jan 2023 at 02:10, Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote:
>>
>>
>>
>> On 18.01.2023 21:34, Bhupesh Sharma wrote:
>>> Add CPU idle-state nodes and power-domains in Qualcomm sm6115 SoC dtsi.
>>>
>>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
>>> ---
[...]
>>> +
>>> + domain-idle-states {
>>> + CLUSTER_SLEEP_0: cluster-sleep-0 {
>>> + compatible = "domain-idle-state";
>>> + idle-state-name = "cluster-power-collapse";
>>> + arm,psci-suspend-param = <0x41000043>;
>>> + entry-latency-us = <800>;
>>> + exit-latency-us = <2118>;
>>> + min-residency-us = <7376>;
>> These values vary per cluster, see qcom,pm-cluster-level@2 in the
>> file linked above.. We should either split that, or at least take
>> max() of each value between the two nodes to make sure the sleep
>> state is exited properly on both types of cores.
>
> Ack to both the above observations. Will send a fixed v2 shortly.
In doing so, please also add support for D3G cluster sleep states
as well, it sounds beneficial to have a middleground between a total
power collapse and a simple wfi.
Konrad
>
> Thanks,
> Bhupesh
>
>>> + };
>>> + };
>>> };
>>>
>>> firmware {
>>> @@ -191,6 +242,59 @@ pmu {
>>> psci {
>>> compatible = "arm,psci-1.0";
>>> method = "smc";
>>> +
>>> + CPU_PD0: power-domain-cpu0 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CPU_PD1: power-domain-cpu1 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CPU_PD2: power-domain-cpu2 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CPU_PD3: power-domain-cpu3 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CPU_PD4: power-domain-cpu4 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CPU_PD5: power-domain-cpu5 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CPU_PD6: power-domain-cpu6 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CPU_PD7: power-domain-cpu7 {
>>> + #power-domain-cells = <0>;
>>> + power-domains = <&CLUSTER_PD>;
>>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>>> + };
>>> +
>>> + CLUSTER_PD: power-domain-cpu-cluster0 {
>>> + #power-domain-cells = <0>;
>>> + domain-idle-states = <&CLUSTER_SLEEP_0>;
>>> + };
>>> };
>>>
>>> reserved_memory: reserved-memory {
