On Tue, 21 Feb 2023 17:23:36 +0000, Conor Dooley wrote: > Hey Hal, > > On Tue, Feb 21, 2023 at 10:46:35AM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@xxxxxxxx> >> >> Add bindings for the system clock and reset generator (SYSCRG) on the >> JH7110 RISC-V SoC by StarFive Ltd. >> >> Reviewed-by: Rob Herring <robh@xxxxxxxxxx> >> Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> >> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> > >> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> new file mode 100644 >> index 000000000000..ec81504dcb27 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> @@ -0,0 +1,80 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 System Clock and Reset Generator >> + >> +maintainers: >> + - Emil Renner Berthing <kernel@xxxxxxxx> >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-syscrg >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Main Oscillator (24 MHz) >> + - description: GMAC1 RMII reference >> + - description: GMAC1 RGMII RX >> + - description: External I2S TX bit clock >> + - description: External I2S TX left/right channel clock >> + - description: External I2S RX bit clock >> + - description: External I2S RX left/right channel clock >> + - description: External TDM clock >> + - description: External audio master clock > > You didn't reply to the conversation I had with Krzysztof about how to > represent the optional nature of some of these clocks, contained in this > thread here: > https://lore.kernel.org/all/7a7bccb1-4d47-3d32-36e6-4aab7b5b8dad@xxxxxxxxxxxxxxxx/ > > What happens to the gmac1 mux if only one of the input clocks is > provided? > And I mean what does the hardware do, not the software representation of > that mux in the driver. In hardware, just providing the required input clocks is enough. Refer to the following link for the required clocks. Thanks. https://lore.kernel.org/all/c0472d7f-56fe-3e91-e0a0-49ee51700b5d@xxxxxxxxxxxxxxxx/ Best regards, Hal > >> + >> + clock-names: >> + items: >> + - const: osc >> + - const: gmac1_rmii_refin >> + - const: gmac1_rgmii_rxin >> + - const: i2stx_bclk_ext >> + - const: i2stx_lrck_ext >> + - const: i2srx_bclk_ext >> + - const: i2srx_lrck_ext >> + - const: tdm_ext >> + - const: mclk_ext
