On 21/02/2023 03:46, Hal Feng wrote: > From: Emil Renner Berthing <kernel@xxxxxxxx> > > Add bindings for the system clock and reset generator (SYSCRG) on the > JH7110 RISC-V SoC by StarFive Ltd. > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> > Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> I don't know what is happening here as neither this nor other patchset explains anything. Please stop writing what you do in the patches, but explain why. What is easy to get. (...) > + > +#define JH7110_SYSCLK_PLL0_OUT 190 > +#define JH7110_SYSCLK_PLL1_OUT 191 > +#define JH7110_SYSCLK_PLL2_OUT 192 NAK. Do not add incorrect bindings just to remove it THE SAME TIME. Best regards, Krzysztof
