The apmixed clocks of MT7981 and MT7986 are identical. In order to de-duplicate both clock drivers, start with putting apmixed into a header files of its own, so it can be used by both SoCs. Propagate this change also to mt7986a.dtsi which is the only user. Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 + drivers/clk/mediatek/clk-mt7986-apmixed.c | 2 +- .../clock/mediatek,filogic-apmixed.h | 21 +++++++++++++++++++ .../dt-bindings/clock/mediatek,mt7981-clk.h | 10 --------- .../dt-bindings/clock/mediatek,mt7986-clk.h | 11 ---------- 5 files changed, 23 insertions(+), 22 deletions(-) create mode 100644 include/dt-bindings/clock/mediatek,filogic-apmixed.h diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 5159ff8673501..051a3e95f3141 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mediatek,mt7986-clk.h> #include <dt-bindings/clock/mediatek,ethsys.h> +#include <dt-bindings/clock/mediatek,filogic-apmixed.h> #include <dt-bindings/reset/mt7986-resets.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/thermal/thermal.h> diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c index 6767e9c438866..89112c1c476e1 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -16,7 +16,7 @@ #include "clk-mux.h" #include "clk-pll.h" -#include <dt-bindings/clock/mt7986-clk.h> +#include <dt-bindings/clock/mediatek,filogic-apmixed.h> #include <linux/clk.h> #define MT7986_PLL_FMAX (2500UL * MHZ) diff --git a/include/dt-bindings/clock/mediatek,filogic-apmixed.h b/include/dt-bindings/clock/mediatek,filogic-apmixed.h new file mode 100644 index 0000000000000..459a402c76f66 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,filogic-apmixed.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih <sam.shih@xxxxxxxxxxxx> + */ + +#ifndef _DT_BINDINGS_CLK_MEDIATEK_FILOGIC_APMIXED_H +#define _DT_BINDINGS_CLK_MEDIATEK_FILOGIC_APMIXED_H + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt7981-clk.h b/include/dt-bindings/clock/mediatek,mt7981-clk.h index 8f39248dcd34d..c3546daae7717 100644 --- a/include/dt-bindings/clock/mediatek,mt7981-clk.h +++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h @@ -184,14 +184,4 @@ #define CLK_INFRA_IPCIER_CK 59 #define CLK_INFRA_IPCIEB_CK 60 -/* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_NET2PLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_SGMPLL 3 -#define CLK_APMIXED_WEDMCUPLL 4 -#define CLK_APMIXED_NET1PLL 5 -#define CLK_APMIXED_MPLL 6 -#define CLK_APMIXED_APLL2 7 - #endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/include/dt-bindings/clock/mediatek,mt7986-clk.h b/include/dt-bindings/clock/mediatek,mt7986-clk.h index 67179a18589a9..a307ae4960077 100644 --- a/include/dt-bindings/clock/mediatek,mt7986-clk.h +++ b/include/dt-bindings/clock/mediatek,mt7986-clk.h @@ -7,17 +7,6 @@ #ifndef _DT_BINDINGS_CLK_MT7986_H #define _DT_BINDINGS_CLK_MT7986_H -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_NET2PLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_SGMPLL 3 -#define CLK_APMIXED_WEDMCUPLL 4 -#define CLK_APMIXED_NET1PLL 5 -#define CLK_APMIXED_MPLL 6 -#define CLK_APMIXED_APLL2 7 - /* TOPCKGEN */ #define CLK_TOP_XTAL 0 -- 2.39.2
