On 22.02.2023 16:32, Manivannan Sadhasivam wrote:
> There is only one PCIe PHY in this SoC, so there is no need to add an
> index to the suffix. This also matches the naming convention of the PCIe
> controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +-
> arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
> index ac8b4626ae9a..b7ee0237608f 100644
> --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
> +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
> @@ -242,7 +242,7 @@ &ipa {
> memory-region = <&ipa_fw_mem>;
> };
>
> -&pcie0_phy {
> +&pcie_phy {
> status = "okay";
>
> vdda-phy-supply = <&vreg_l1e_bb_1p2>;
> diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
> index e84ca795cae6..a1f4a7b0904a 100644
> --- a/arch/arm/boot/dts/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
> @@ -334,7 +334,7 @@ pcie_ep: pcie-ep@1c00000 {
> resets = <&gcc GCC_PCIE_BCR>;
> reset-names = "core";
> power-domains = <&gcc PCIE_GDSC>;
> - phys = <&pcie0_lane>;
> + phys = <&pcie_lane>;
> phy-names = "pciephy";
> max-link-speed = <3>;
> num-lanes = <2>;
> @@ -342,7 +342,7 @@ pcie_ep: pcie-ep@1c00000 {
> status = "disabled";
> };
>
> - pcie0_phy: phy@1c07000 {
> + pcie_phy: phy@1c07000 {
> compatible = "qcom,sdx55-qmp-pcie-phy";
> reg = <0x01c07000 0x1c4>;
> #address-cells = <1>;
> @@ -362,7 +362,7 @@ pcie0_phy: phy@1c07000 {
>
> status = "disabled";
>
> - pcie0_lane: lanes@1c06000 {
> + pcie_lane: lanes@1c06000 {
> reg = <0x01c06000 0x104>, /* tx0 */
> <0x01c06200 0x328>, /* rx0 */
> <0x01c07200 0x1e8>, /* pcs */
