On 21/02/2023 09:33, Xingyu Wu wrote: > Add bindings for the Video-Output clock and reset generator (VOUTCRG) > on the JH7110 RISC-V SoC by StarFive Ltd. > > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > --- > .../clock/starfive,jh7110-voutcrg.yaml | 96 +++++++++++++++++++ > .../dt-bindings/clock/starfive,jh7110-crg.h | 22 +++++ > .../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++ > 3 files changed, 134 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
