On Tue, Feb 14, 2023 at 1:26 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > > On Mon, Feb 06, 2023 at 12:14:53PM -0800, Evan Green wrote: > > From: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > > > > This key allows device trees to specify the performance of misaligned > > accesses to main memory regions from each CPU in the system. > > > > Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > > Signed-off-by: Evan Green <evan@xxxxxxxxxxxx> > > --- > > > > (no changes since v1) > > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index c6720764e765..2c09bd6f2927 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -85,6 +85,21 @@ properties: > > $ref: "/schemas/types.yaml#/definitions/string" > > pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ > > > > + riscv,misaligned-access-performance: > > + description: > > + Identifies the performance of misaligned memory accesses to main memory > > + regions. There are three flavors of unaligned access performance: "emulated" > > Is the performance: emulated the source of the dt_binding_check issues? > And the fix is as simple as: > - description: > + description: | > ? Yep, I can pass cleanly with that change. Thanks!
