On Mon, Feb 06, 2023 at 11:26:16PM +0200, Abel Vesa wrote:
> Add the SM8550 both g4 and g3 configurations. In addition, there is a
> new "lane shared" table that needs to be configured for g4, along with
> the No-CSR list of resets. The no-CSR allows resetting the PHY without
> actually dropping the PHY configuration. The no-CSR needs to be
> deasserted only after the PHY has been configured and the PLL has
> stabilized.
>
> Co-developed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> @@ -2370,6 +2690,12 @@ static int qmp_pcie_power_on(struct phy *phy)
> if (ret)
> return ret;
>
> + ret = reset_control_deassert(qmp->nocsr_reset);
> + if (ret) {
> + dev_err(qmp->dev, "no-csr reset deassert failed\n");
> + goto err_disable_pipe_clk;
> + }
> +
> /* Pull PHY out of reset state */
> qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>
> @@ -2503,6 +2829,13 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
> if (ret)
> return dev_err_probe(dev, ret, "failed to get resets\n");
>
> + if (cfg->has_nocsr_reset) {
> + qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
> + if (IS_ERR(qmp->nocsr_reset))
> + return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
> + "failed to get no-CSR reset\n");
Nit: You're still using uppercase CSR here and lowercase elsewhere.
> + }
> +
> return 0;
> }
Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
