Hi Marcel,
Am Donnerstag, 26. Januar 2023, 12:08:28 CET schrieb Marcel Ziswiler:
> From: Joakim Zhang <qiangqing.zhang@xxxxxxx>
>
> Add FlexCAN decive in adma subsystem.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@xxxxxxx>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
On TQMa8XQP (i.MX8QXP) using flexcan1 and flexcan2:
Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
Best regards,
Alexander
> ---
>
> (no changes since v4)
>
> Changes in v4:
> - New patch combining the following downstream patches:
> commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma")
> commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for
> CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new
> clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for
> CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN
> fsl,clk-source and fsl,scu-index property")
>
> .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index
> 6ccf926b77a5..2dce8f2ee3ea 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> @@ -298,6 +298,65 @@ adc1: adc@5a890000 {
> status = "disabled";
> };
>
> + flexcan1: can@5a8d0000 {
> + compatible = "fsl,imx8qm-flexcan";
> + reg = <0x5a8d0000 0x10000>;
> + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&can0_lpcg 1>,
> + <&can0_lpcg 0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <40000000>;
> + power-domains = <&pd IMX_SC_R_CAN_0>;
> + /* SLSlice[4] */
> + fsl,clk-source = /bits/ 8 <0>;
> + fsl,scu-index = /bits/ 8 <0>;
> + status = "disabled";
> + };
> +
> + flexcan2: can@5a8e0000 {
> + compatible = "fsl,imx8qm-flexcan";
> + reg = <0x5a8e0000 0x10000>;
> + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + /* CAN0 clock and PD is shared among all CAN instances as
> + * CAN1 shares CAN0's clock and to enable CAN0's clock it
> + * has to be powered on.
> + */
> + clocks = <&can0_lpcg 1>,
> + <&can0_lpcg 0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <40000000>;
> + power-domains = <&pd IMX_SC_R_CAN_1>;
> + /* SLSlice[4] */
> + fsl,clk-source = /bits/ 8 <0>;
> + fsl,scu-index = /bits/ 8 <1>;
> + status = "disabled";
> + };
> +
> + flexcan3: can@5a8f0000 {
> + compatible = "fsl,imx8qm-flexcan";
> + reg = <0x5a8f0000 0x10000>;
> + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + /* CAN0 clock and PD is shared among all CAN instances as
> + * CAN2 shares CAN0's clock and to enable CAN0's clock it
> + * has to be powered on.
> + */
> + clocks = <&can0_lpcg 1>,
> + <&can0_lpcg 0>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <40000000>;
> + power-domains = <&pd IMX_SC_R_CAN_2>;
> + /* SLSlice[4] */
> + fsl,clk-source = /bits/ 8 <0>;
> + fsl,scu-index = /bits/ 8 <2>;
> + status = "disabled";
> + };
> +
> i2c0_lpcg: clock-controller@5ac00000 {
> compatible = "fsl,imx8qxp-lpcg";
> reg = <0x5ac00000 0x10000>;
> @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 {
> "adc1_lpcg_ipg_clk";
> power-domains = <&pd IMX_SC_R_ADC_1>;
> };
> +
> + can0_lpcg: clock-controller@5acd0000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5acd0000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
> + <&dma_ipg_clk>, <&dma_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
> + clock-output-names = "can0_lpcg_pe_clk",
> + "can0_lpcg_ipg_clk",
> + "can0_lpcg_chi_clk";
> + power-domains = <&pd IMX_SC_R_CAN_0>;
> + };
> };
