On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
arch/arm/boot/dts/imx6dl-plybas.dts | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts
index c52e6caf3996..e98046eea7a4 100644
--- a/arch/arm/boot/dts/imx6dl-plybas.dts
+++ b/arch/arm/boot/dts/imx6dl-plybas.dts
@@ -75,6 +75,7 @@ clk50m_phy: phy-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_5v0: regulator-5v0 {
@@ -99,6 +100,13 @@ &can2 {
status = "okay";
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -116,10 +124,6 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rgmii_phy>;
status = "okay";
--
2.30.2
