On Fri, Jan 13, 2023, at 17:44, Robert Marko wrote:
> IPQ8074 comes in 2 silicon versions:
> * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
>
> v2 is the final and production version that is actually supported by the
> kernel, however it looks like PCIe related nodes were added for the v1 SoC.
>
> Finish the PCIe fixup by using the correct compatible, adding missing ATU
> register space, declaring max-link-speed, use correct ranges, add missing
> clocks and resets.
>
> Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
> Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
I was reading through the pull request today and saw this patch
along with the Gen2 one:
> @@ -871,9 +873,9 @@ pcie0: pci@20000000 {
> phy-names = "pciephy";
>
> ranges = <0x81000000 0 0x20200000 0x20200000
> - 0 0x100000 /* downstream I/O */
> + 0 0x10000>, /* downstream I/O */
Fixing the length here seems fine, but the bus-side address
still looks wrong: 0x20200000 is way outside of the usual
port ranges from 0 to 0x10000 on the local bus.
> - 0x82000000 0 0x20300000 0x20300000
> - 0 0xd00000>; /* non-prefetchable memory */
> + <0x82000000 0 0x20220000 0x20220000
> + 0 0xfde0000>; /* non-prefetchable memory */
I see the total size of the memory space is under 256MB. Are you
sure that there is no 64-bit BAR in addition to this?
I also see commit 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add
PCIe PHYs and controllers nodes") introduce the same broken
I/O port range (oversized 1MB space wiht an identity map) for a
new SoC. This should probably be fixed as well, along with
reviewing the other ones.
Has the I/O space mapping on any of these actually been tested,
or just copied from one SoC to another? Very few devices actually
use I/O space, so it wouldn't be surprising if it never worked
in the first place.
Arnd
