On Thu, Jan 19, 2023 at 05:35:08PM +0200, Abel Vesa wrote:
> On 23-01-19 19:51:55, Manivannan Sadhasivam wrote:
> > On Thu, Jan 19, 2023 at 04:04:51PM +0200, Abel Vesa wrote:
> > > Add compatible for both PCIe found on SM8550.
> > > Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
> > >
> > > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> >
> > Reviewed-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> >
> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> > > ---
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 77e5dc7b88ad..30f74bc51dbf 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 {
> > >
> > > /* 6 clocks typically, 7 for sm8250 */
> >
> > Now this comment is outdated ;)
> >
>
> Fair point. I'll wait for some more comments before
> I'll send a new version.
The comment is still correct, as several of these clocks are optional
and platform dependant. There's strictly no need to update it as part
of this patch.
> > > struct qcom_pcie_resources_2_7_0 {
> > > - struct clk_bulk_data clks[12];
> > > + struct clk_bulk_data clks[13];
> > > int num_clks;
> > > struct regulator_bulk_data supplies[2];
> > > struct reset_control *pci_reset;
> > > @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> > > res->clks[idx++].id = "noc_aggr_4";
> > > res->clks[idx++].id = "noc_aggr_south_sf";
> > > res->clks[idx++].id = "cnoc_qx";
> > > + res->clks[idx++].id = "cnoc_sf_axi";
Johan
