Hi Arnd, thanks for the fast response. Am Donnerstag, 19. Januar 2023, 16:09:05 CET schrieb Arnd Bergmann: > On Thu, Jan 19, 2023, at 15:42, Alexander Stein wrote: > > This is necessary to support PCIe on LS1021A. > > > > Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > > Can you explain why this is actually required? I can see that the > ranges in the PCIe device point to a high address (0x4000000000, > 2^40), but I can't tell if this is hardwired in the SoC or a > setting that is applied by software (either the bootloader or > the PCIe driver). The RM ([1]) memory map (Table 2-1) says that 'PCI Express 1' is located at '400000_0000', 'PCI Express 2' at '480000_0000', so I assume this is hardcoded in SoC. It also explicitly lists in that table PCIe 1&2 is only accessible with 40-bit addressing. > If you can reprogram the memory map, I would expect this to fit > easily into the 32-bit address space, with 1GB for DDR3 memory > and 1GB for PCIe BARs. I'm not sure which part of memory map you can reprogram and where, but I guess this is fixed on this SoC. > I don't mind having a defconfig with LPAE enabled, I think this > can be done using a Makefile target that applies a config > fragment on top of the normal multi_v7_defconfig, you can find > some examples in arch/powerpc/configs/*.config. Ah, nice. This can be a good starter. Thanks. Best regards, Alexander [1] https://www.nxp.com/webapp/Download?colCode=LS1021ARM
