On Thu, Jan 19, 2023, at 15:42, Alexander Stein wrote: > This is necessary to support PCIe on LS1021A. > > Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> Can you explain why this is actually required? I can see that the ranges in the PCIe device point to a high address (0x4000000000, 2^40), but I can't tell if this is hardwired in the SoC or a setting that is applied by software (either the bootloader or the PCIe driver). If you can reprogram the memory map, I would expect this to fit easily into the 32-bit address space, with 1GB for DDR3 memory and 1GB for PCIe BARs. I don't mind having a defconfig with LPAE enabled, I think this can be done using a Makefile target that applies a config fragment on top of the normal multi_v7_defconfig, you can find some examples in arch/powerpc/configs/*.config. Arnd
