On 17.01.2023 23:58, Dmitry Baryshkov wrote:
> The vendor kernel uses RPM_SMD_XO_CLK_SRC clock as an CXO clock rather
> than using the RPM_SMD_BB_CLK1 directly. Follow this example and switch
> msm8996.dtsi to use RPM_SMD_XO_CLK_SRC clock instead of RPM_SMB_BB_CLK1.
>
> Fixes: 2b8c9c77c268 ("arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1")
> Suggested-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index a8544c4158ac..150d13c0f4b8 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -713,7 +713,7 @@ gcc: clock-controller@300000 {
> #power-domain-cells = <1>;
> reg = <0x00300000 0x90000>;
>
> - clocks = <&rpmcc RPM_SMD_BB_CLK1>,
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> <&rpmcc RPM_SMD_LN_BB_CLK>,
> <&sleep_clk>,
> <&pciephy_0>,
> @@ -1055,7 +1055,7 @@ dsi0_phy: phy@994400 {
> #clock-cells = <1>;
> #phy-cells = <0>;
>
> - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
> + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
> clock-names = "iface", "ref";
> status = "disabled";
> };
> @@ -1123,7 +1123,7 @@ dsi1_phy: phy@996400 {
> #clock-cells = <1>;
> #phy-cells = <0>;
>
> - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
> + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
> clock-names = "iface", "ref";
> status = "disabled";
> };
> @@ -2952,7 +2952,7 @@ kryocc: clock-controller@6400000 {
> reg = <0x06400000 0x90000>;
>
> clock-names = "xo", "sys_apcs_aux";
> - clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>;
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&apcs_glb>;
>
> #clock-cells = <1>;
> };
> @@ -3071,7 +3071,7 @@ sdhc1: mmc@7464900 {
> clock-names = "iface", "core", "xo";
> clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> <&gcc GCC_SDCC1_APPS_CLK>,
> - <&rpmcc RPM_SMD_BB_CLK1>;
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> resets = <&gcc GCC_SDCC1_BCR>;
>
> pinctrl-names = "default", "sleep";
> @@ -3095,7 +3095,7 @@ sdhc2: mmc@74a4900 {
> clock-names = "iface", "core", "xo";
> clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> <&gcc GCC_SDCC2_APPS_CLK>,
> - <&rpmcc RPM_SMD_BB_CLK1>;
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> resets = <&gcc GCC_SDCC2_BCR>;
>
> pinctrl-names = "default", "sleep";
> @@ -3417,7 +3417,7 @@ adsp_pil: remoteproc@9300000 {
> interrupt-names = "wdog", "fatal", "ready",
> "handover", "stop-ack";
>
> - clocks = <&rpmcc RPM_SMD_BB_CLK1>;
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
> clock-names = "xo";
>
> memory-region = <&adsp_mem>;
