On Wed, 04 Jan 2023 18:05:13 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> RISC-V uses the same generic topology code as arm64 & while there
> currently exists no binding for cpu-capacity on RISC-V, the code paths
> can be hit if the property is present.
>
> Move the documentation of cpu-capacity to a shared location, ahead of
> defining a binding for capacity-dmips-mhz on RISC-V. Update some
> references to this document in the process.
>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> ---
> I wasn't sure what to do with reference [1], but since the property will
> be the same on RISC-V, I left it as is.
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 2 +-
> .../devicetree/bindings/{arm => cpu}/cpu-capacity.txt | 4 ++--
> Documentation/scheduler/sched-capacity.rst | 2 +-
> Documentation/translations/zh_CN/scheduler/sched-capacity.rst | 2 +-
> 4 files changed, 5 insertions(+), 5 deletions(-)
> rename Documentation/devicetree/bindings/{arm => cpu}/cpu-capacity.txt (98%)
>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
