On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > describes the L2 cache block. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > --- > v5 -> v6 > * Included RB tag from Geert I think not! > v4 -> v5 > * Dropped L2 cache configuration properties > * Dropped PMA configuration properties > * Ordered the required list to match the properties list > > RFC v3 -> v4 > * Dropped l2 cache configuration parameters > * s/larger/large > * Added minItems/maxItems for andestech,pma-regions > --- > .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > new file mode 100644 > index 000000000000..9f0be4835ad7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Andestech AX45MP L2 Cache Controller > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > + > +description: > + A level-2 cache (L2C) is used to improve the system performance by providing > + a large amount of cache line entries and reasonable access delays. The L2C > + is shared between cores, and a non-inclusive non-exclusive policy is used. > + > +select: > + properties: > + compatible: > + contains: > + enum: > + - andestech,ax45mp-cache > + > + required: > + - compatible > + > +properties: > + compatible: > + items: > + - const: andestech,ax45mp-cache > + - const: cache You might find value in a specific compatible for your SoC & enforce constraints for it. Or you might not & I don't care either way :) Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Thanks, Conor.
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