On Fri, Jan 06, 2023 at 06:55:23PM +0000, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Add required ports of the Alternative scheme for Andes CPU cores. > > I/O Coherence Port (IOCP) provides an AXI interface for connecting external > non-caching masters, such as DMA controllers. IOCP is a specification > option and is disabled on the Renesas RZ/Five SoC due to this reason cache > management needs a software workaround. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > v5 -> v6 > * Dropped patching alternative and now just probing IOCP > > v4 -> v5 > * Sorted the Kconfig/Makefile/Switch based on Core name > * Added a comments > * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if > CMO needs to be applied. Is there a way we can access the DTB while patching > as we can drop this SBI EXT ID and add a DT property instead for cmo? > > RFC v3 -> v4 > * New patch > --- > arch/riscv/Kconfig.erratas | 22 +++++++++ > arch/riscv/errata/Makefile | 1 + > arch/riscv/errata/andes/Makefile | 1 + > arch/riscv/errata/andes/errata.c | 71 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/alternative.h | 3 ++ > arch/riscv/kernel/alternative.c | 5 ++ > 6 files changed, 103 insertions(+) > create mode 100644 arch/riscv/errata/andes/Makefile > create mode 100644 arch/riscv/errata/andes/errata.c > > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > index 69621ae6d647..f0f0c1abd52b 100644 > --- a/arch/riscv/Kconfig.erratas > +++ b/arch/riscv/Kconfig.erratas > @@ -1,5 +1,27 @@ > menu "CPU errata selection" > > +config ERRATA_ANDES > + bool "Andes AX45MP errata" > + depends on !XIP_KERNEL > + select RISCV_ALTERNATIVE > + help > + All Andes errata Kconfig depend on this Kconfig. Disabling > + this Kconfig will disable all Andes errata. Please say "Y" > + here if your platform uses Andes CPU cores. > + > + Otherwise, please say "N" here to avoid unnecessary overhead. > + > +config ERRATA_ANDES_CMO > + bool "Apply Andes cache management errata" > + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 > + select RISCV_DMA_NONCOHERENT > + default y > + help > + This will apply the cache management errata to handle the > + non-standard handling on non-coherent operations on Andes cores. > + > + If you don't know what to do here, say "Y". Ideally we would not need errata to turn this stuff on at all, but, as you pointed out to me off-list, arch_setup_dma_ops() complains if we have not set up. I'm happy to commit to trying to sort that out in follow on work w/ MPFS, since in that case it really isn't errata, and not require it for this series as you do fit that particular bill IMO. Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Thanks, Conor.
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