RE: [PATCH v3 11/13] v4l: xilinx: Add Xilinx Video IP core

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Laurent,

> -----Original Message-----
> From: Laurent Pinchart [mailto:laurent.pinchart@xxxxxxxxxxxxxxxx]
> Sent: Wednesday, November 05, 2014 10:36 AM
> To: linux-media@xxxxxxxxxxxxxxx
> Cc: Michal Simek; Chris Kohn; Hyun Kwon; devicetree@xxxxxxxxxxxxxxx
> Subject: [PATCH v3 11/13] v4l: xilinx: Add Xilinx Video IP core
>
> Xilinx platforms have no hardwired video capture or video processing
> interface. Users create capture and memory to memory processing
> pipelines in the FPGA fabric to suit their particular needs, by
> instantiating video IP cores from a large library.
>
> The Xilinx Video IP core is a framework that models a video pipeline
> described in the device tree and expose the pipeline to userspace
> through the media controller and V4L2 APIs.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> Signed-off-by: Hyun Kwon <hyun.kwon@xxxxxxxxxx>
> Signed-off-by: Radhey Shyam Pandey <radheys@xxxxxxxxxx>
> Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx>
>
> ---
>
> I'd appreciate if DT reviewers could have a look at the xlnx,video-format and
> xlnx,video-width properties if nothing else.
>
> Changes since v2:
>
> - Remove explicit trailing \0 after snprintf
> - Don't hardcode colorspace

I've split these two up based on the individual patches in the tree you pointed me to yesterday. The first one I squashed into

v4l: xilinx: dma: Fix querycap capabilities and bus_info reporting

for the colorspace I created a new patch. I don't want to take credit for it, so if you can send me a patch I'll apply it to my local branch.

Other than that, it's working fine on my end.

Cheers,
Chris


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