Enable the OSM block responsible for scaling the L3 cache.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---
v1 -> v2:
No changes
arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index e71ffc31d41e..893a1ffb5e3d 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -2040,6 +2040,16 @@ apps_bcm_voter: bcm-voter {
};
};
+ osm_l3: interconnect@18321000 {
+ compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
+ reg = <0x0 0x18321000 0x0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
--
2.39.0
