On Tue, Jan 3, 2023, at 22:04, Conor Dooley wrote: > From: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> > > SiFive L2 cache controller can flush L2 cache. Expose this capability via > driver. > > Signed-off-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> > [Conor: rebase on top of move to cache subsystem] > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > This commit needs more work, and a way to enable it from errata. I've > not gone and done this as PolarFire SoC has archid etc all set to zero. > So we need to go figure out a workaround for this, before adding in > errata enabling code for this. I've included it here as a second user of > the cache management stuff, since what's currently upstream for the > ccache driver does not do any cache management. > --- > drivers/cache/sifive_ccache.c | 45 +++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) My feeling here is that the cacheflush code is unrelated to the EDAC code and it should just be a separate file. From what I can tell, all of the existing contents of this file can simply get merged into drivers/edac/sifive_edac.c, with the newly added code becoming a standalone driver. Arnd