Hello, This series adds GIC-ITS support to SM8450 PCIe controllers for signalling the MSIs received from endpoint devices to the CPU cores. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. This series has been tested on SM8450 based dev board that works using an out-of-tree dts where the MSIs from endpoint devices are distributed across the CPU cores. Thanks, Mani Changes in v2: * Reworded the commit messages as per Lorenzo's comments * Rebased on top of v6.2-rc1 Changes in v2: * Swapped the Device ID for PCIe0 as it causes same issue as PCIe1 * Removed the definition of msi-map and msi-map-mask from binding * Added Ack from Krzysztof Manivannan Sadhasivam (3): dt-bindings: PCI: qcom: Update maintainers dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1 .../devicetree/bindings/pci/qcom,pcie.yaml | 14 +++++++++---- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 +++++++++++++------ 2 files changed, 24 insertions(+), 10 deletions(-) -- 2.25.1
