Add the timer node for the Starfive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c22e8f1d2640..3936c7c0c962 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -356,6 +356,28 @@ gpioa: gpio@17020000 {
#gpio-cells = <2>;
};
+ timer: timer@13050000 {
+ compatible = "starfive,jh7110-timers";
+ reg = <0x0 0x13050000 0x0 0x10000>;
+ interrupts = <69>, <70>, <71> ,<72>;
+ interrupt-names = "timer0", "timer1", "timer2", "timer3";
+ clocks = <&syscrg JH7110_SYSCLK_TIMER0>,
+ <&syscrg JH7110_SYSCLK_TIMER1>,
+ <&syscrg JH7110_SYSCLK_TIMER2>,
+ <&syscrg JH7110_SYSCLK_TIMER3>,
+ <&syscrg JH7110_SYSCLK_TIMER_APB>;
+ clock-names = "timer0", "timer1",
+ "timer2", "timer3", "apb";
+ resets = <&syscrg JH7110_SYSRST_TIMER0>,
+ <&syscrg JH7110_SYSRST_TIMER1>,
+ <&syscrg JH7110_SYSRST_TIMER2>,
+ <&syscrg JH7110_SYSRST_TIMER3>,
+ <&syscrg JH7110_SYSRST_TIMER_APB>;
+ reset-names = "timer0", "timer1",
+ "timer2", "timer3", "apb";
+ clock-frequency = <24000000>;
+ };
+
uart0: serial@10000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x10000000 0x0 0x10000>;
--
2.25.1
