Il 22/12/22 16:51, AngeloGioacchino Del Regno ha scritto:
This series adds support for Frequency Hopping (FHCTL) on more MediaTek
SoCs, specifically, MT6795, MT8173, MT8192 and MT8195.
In order to support older platforms like MT6795 and MT8173 it was
necessary to add a new register layout that is ever-so-slightly
different from the one that was previously introduced for MT8186.
Since the new layout refers to older SoCs, the one valid for MT8186
and newer SoCs was renamed to be a "v2" layout, while the new one
for older chips gets the "v1" name.
Note: These commits won't change any behavior unless FHCTL gets
explicitly enabled and configured in devicetrees.
Forgot to write in the cover letter that this series can be applied on top
of [1], but that's a dependency only because that big cleanup moves things
around (hence these commits won't apply if not on top of [1]).
[1]:
https://lore.kernel.org/lkml/20221222114857.120060-1-angelogioacchino.delregno@xxxxxxxxxxxxx
Cheers,
Angelo
AngeloGioacchino Del Regno (6):
clk: mediatek: fhctl: Add support for older fhctl register layout
dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795,
MT8173/92/95
clk: mediatek: mt6795: Add support for frequency hopping through FHCTL
clk: mediatek: mt8173: Add support for frequency hopping through FHCTL
clk: mediatek: mt8192: Add support for frequency hopping through FHCTL
clk: mediatek: mt8195: Add support for frequency hopping through FHCTL
.../bindings/clock/mediatek,mt8186-fhctl.yaml | 7 +-
drivers/clk/mediatek/clk-fhctl.c | 26 ++++++-
drivers/clk/mediatek/clk-fhctl.h | 9 ++-
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 63 ++++++++++++++++-
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 65 ++++++++++++++++-
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +
drivers/clk/mediatek/clk-mt8192.c | 67 +++++++++++++++++-
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 ++++++++++++++++++-
drivers/clk/mediatek/clk-pllfh.c | 23 +++++--
drivers/clk/mediatek/clk-pllfh.h | 1 +
10 files changed, 311 insertions(+), 21 deletions(-)
