On 17.12.2022 01:17, Dmitry Baryshkov wrote:
> The QCS404 uses 28nm LPM DSI PHY, which registers dsi0pll and
> dsi0pllbyte clocks. Fix all DSI PHY clock names used as parents inside
> the GCC driver.
>
> Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/clk/qcom/gcc-qcs404.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index c48326da1bb3..23562096298d 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -115,7 +115,7 @@ static const struct parent_map gcc_parent_map_5[] = {
>
> static const char * const gcc_parent_names_5[] = {
> "cxo",
> - "dsi0pll_byteclk_src",
> + "dsi0pllbyte",
> /* "gpll0_out_aux", */
> "core_bi_pll_test_se",
> };
> @@ -129,7 +129,7 @@ static const struct parent_map gcc_parent_map_6[] = {
>
> static const char * const gcc_parent_names_6[] = {
> "cxo",
> - "dsi0_phy_pll_out_byteclk",
> + "dsi0pllbyte",
> /* "gpll0_out_aux", */
> "core_bi_pll_test_se",
> };
> @@ -175,7 +175,7 @@ static const struct parent_map gcc_parent_map_9[] = {
> static const char * const gcc_parent_names_9[] = {
> "cxo",
> "gpll0_out_main",
> - "dsi0_phy_pll_out_dsiclk",
> + "dsi0pll",
> "gpll6_out_aux",
> "core_bi_pll_test_se",
> };
> @@ -213,7 +213,7 @@ static const struct parent_map gcc_parent_map_12[] = {
>
> static const char * const gcc_parent_names_12[] = {
> "cxo",
> - "dsi0pll_pclk_src",
> + "dsi0pll",
> /* "gpll0_out_aux", */
> "core_bi_pll_test_se",
> };
