Add support for Motorcomm Technology YT8531 10/100/1000 Ethernet PHY. The document describe details of clock delay train configuration. Signed-off-by: Yanhong Wang <yanhong.wang@xxxxxxxxxxxxxxxx> --- .../bindings/net/motorcomm,yt8531.yaml | 111 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/motorcomm,yt8531.yaml diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8531.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8531.yaml new file mode 100644 index 000000000000..c5b8a09a78bb --- /dev/null +++ b/Documentation/devicetree/bindings/net/motorcomm,yt8531.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/motorcomm,yt8531.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Motorcomm YT8531 Gigabit Ethernet PHY + +maintainers: + - Yanhong Wang <yanhong.wang@xxxxxxxxxxxxxxxx> + +select: + properties: + $nodename: + pattern: "^ethernet-phy(@[a-f0-9]+)?$" + + required: + - $nodename + +properties: + $nodename: + pattern: "^ethernet-phy(@[a-f0-9]+)?$" + + reg: + minimum: 0 + maximum: 31 + description: + The ID number for the PHY. + + rxc_dly_en: + description: | + RGMII Receive PHY Clock Delay defined with fixed 2ns.This is used for + PHY that have configurable RX internal delays. If this property set + to 1, then automatically add 2ns delay pad for Receive PHY clock. + enum: [0, 1] + default: 0 + + rx_delay_sel: + description: | + This is supplement to rxc_dly_en property,and it can + be specified in 150ps(pico seconds) steps. The effective + delay is: 150ps * N. + minimum: 0 + maximum: 15 + default: 0 + + tx_delay_sel_fe: + description: | + RGMII Transmit PHY Clock Delay defined in pico seconds.This is used for + PHY's that have configurable TX internal delays when speed is 100Mbps + or 10Mbps. It can be specified in 150ps steps, the effective delay + is: 150ps * N. + minimum: 0 + maximum: 15 + default: 15 + + tx_delay_sel: + description: | + RGMII Transmit PHY Clock Delay defined in pico seconds.This is used for + PHY's that have configurable TX internal delays when speed is 1000Mbps. + It can be specified in 150ps steps, the effective delay is: 150ps * N. + minimum: 0 + maximum: 15 + default: 1 + + tx_inverted_10: + description: | + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII + Transmit PHY Clock delay train configuration when speed is 10Mbps. + 0: original 1: inverted + enum: [0, 1] + default: 0 + + tx_inverted_100: + description: | + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII + Transmit PHY Clock delay train configuration when speed is 100Mbps. + 0: original 1: inverted + enum: [0, 1] + default: 0 + + tx_inverted_1000: + description: | + Use original or inverted RGMII Transmit PHY Clock to drive the RGMII + Transmit PHY Clock delay train configuration when speed is 1000Mbps. + 0: original 1: inverted + enum: [0, 1] + default: 0 + +required: + - reg + +additionalProperties: true + +examples: + - | + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + + rxc_dly_en = <1>; + tx_delay_sel_fe = <5>; + tx_delay_sel = <0xa>; + tx_inverted_10 = <0x1>; + tx_inverted_100 = <0x1>; + tx_inverted_1000 = <0x1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 166b0009f63c..1ff68b8524d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19609,6 +19609,7 @@ F: include/dt-bindings/clock/starfive* STARFIVE DWMAC GLUE LAYER M: Yanhong Wang <yanhong.wang@xxxxxxxxxxxxxxxx> S: Maintained +F: Documentation/devicetree/bindings/net/motorcomm,yt8531.yaml F: Documentation/devicetree/bindings/net/starfive,jh71x0-dwmac.yaml STARFIVE PINCTRL DRIVER -- 2.17.1
