Re: [PATCH 1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells

[Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>]

Hi Lucas,

Am Dienstag, 13. Dezember 2022, 17:01:09 CET schrieb Lucas Stach:
> The HSIO blk-ctrl has a internal PLL, which can be used as a reference
> clock for the PCIe PHY. Add clock-cells to the binding to allow the
> driver to expose this PLL.
> 
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> ---
>  .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
> b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
> index c29181a9745b..1cc7c2bdf2bb 100644
> ---
> a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
> +++
> b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
> @@ -39,6 +39,9 @@ properties:
>        - const: pcie
>        - const: pcie-phy
> 
> +  '#clock-cells':
> +    const: 1

Rob's bot already noticed the mismatch between this and the example.

Best regards,
Alexander

> +
>    clocks:
>      minItems: 2
>      maxItems: 2
> @@ -85,4 +88,5 @@ examples:
>          power-domain-names = "bus", "usb", "usb-phy1",
>                               "usb-phy2", "pcie", "pcie-phy";
>          #power-domain-cells = <1>;
> +        #clock-cells = <0>;
>      };