Add device nodes for the compare match timer(TIM) channels that are
not assigned to the ISP.
The channels 22 is assigned for clock source and channel 23 for
clock event and rest of the channels are assigned for counter
operation.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 192 +++++++++++++++++++++
1 file changed, 192 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index dcd3a05e54fe..69c1ebc5e0dd 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -135,6 +135,198 @@ sys: system-controller@a3f03000 {
reg = <0 0xa3f03000 0 0x400>;
};
+ tim8: timer@a4000400 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000400 0 0x80>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM8_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim9: timer@a4000480 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000480 0 0x80>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM9_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim10: timer@a4000500 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000500 0 0x80>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM10_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim11: timer@a4000580 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000580 0 0x80>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM11_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim12: timer@a4000600 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000600 0 0x80>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM12_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim13: timer@a4000680 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000680 0 0x80>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM13_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim14: timer@a4000700 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000700 0 0x80>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM14_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim15: timer@a4000780 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000780 0 0x80>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPB_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM15_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim16: timer@a4000800 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000800 0 0x80>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM16_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim17: timer@a4000880 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000880 0 0x80>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM17_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim18: timer@a4000900 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000900 0 0x80>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM18_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim19: timer@a4000980 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000980 0 0x80>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM19_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim20: timer@a4000a00 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000a00 0 0x80>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM20_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim21: timer@a4000a80 {
+ compatible = "renesas,r9a09g011-tim-cnt",
+ "renesas,rzv2m-tim-cnt";
+ reg = <0 0xa4000a80 0 0x80>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM21_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim22: timer@a4000b00 {
+ compatible = "renesas,r9a09g011-tim",
+ "renesas,rzv2m-tim";
+ reg = <0 0xa4000b00 0 0x80>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM22_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
+ tim23: timer@a4000b80 {
+ compatible = "renesas,r9a09g011-tim",
+ "renesas,rzv2m-tim";
+ reg = <0 0xa4000b80 0 0x80>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPC_PCLK>,
+ <&cpg CPG_MOD R9A09G011_TIM23_CLK>;
+ clock-names = "apb", "tim";
+ resets = <&cpg R9A09G011_TIM_GPC_PRESETN>;
+ power-domains = <&cpg>;
+ };
+
pwm8: pwm@a4010400 {
compatible = "renesas,r9a09g011-pwm",
"renesas,rzv2m-pwm";
--
2.25.1
